Personal computers and smart terminals have a central processing unit (CPU) or microprocessor for carrying out arithmetic functions. In addition, these computer devices have a video display processor (VDP) for converting video codes to information for display on a video type monitor. The video codes are stored in a random access memory (RAM) within the personal computer. This memory must also be accessed by the CPU, which generates the digital representation of the images to be displayed. Access by the VDP is supervised by a video display controller (VDC). The video codes supplied to the VDP from the RAM may be ones that can be converted directly to analog video signals in a digital-to-analog conversion. Alternatively, the video codes may be addresses for color map memory, read-outs from which are converted to analog video signals in a digital-to-analog conversion.
In prior-art computer devices of this general type, the VDC has had priority for accessing the RAM; and the CPU, which attempts to access the RAM on a generally irregular basis has had to wait for access when the VDP is accessing the RAM. This has the undesired effect of slowing the operation of the CPU, particularly when the VDP must frequently as well as regularly access the RAM.
McCallister et al. in their U.S. Pat. No. 4,595,917 issued June 17, 1986 and entitled "DATA PROCESSING FOR COMPUTER COLOR GRAPHIC SYSTEM" describe a RAM architecture wherein the memory is divided into n banks, each descriptive of a particular bit plane in the digital codes descriptive of display video. Each bank of memory has an m-bit-wide output port. Here m and n are each positive integers greater than one--e.g., sixteen and four, respectively. Of the n banks of memory, each except one of them reads to a respective parallel-input m-bit-wide latch, thereafter to side-load a respective m-stage shift register. The m-bit-wide outputs of the n banks are serially polled on a regularly recurring basis to side-load all n of the m-stage shift registers. The n shift registers are then simultaneously serially read out at normal pixel scan rate, to generate m successive n-bit-wide codes descriptive of display video.
In an m-pixel display cycle McCallister et al. only have to access the RAM n times, rather than m times--e.g., four times, rather than sixteen. They perform these n accesses per m-pixel display cycle on a regular basis. There is, then, m/n times as good a probability that the CPU will not be called upon to wait because of the accessing of the RAM by the VDP. This speeds up the data processing by the CPU. Supposing the VDP accesses the RAM at a full available access rate, the CPU will be free (m-n)/m of the time to access RAM without waiting.
In my applications Ser. Nos. 710,292 and 710,295 filed Mar. 11, 1985, I describe a RAM structure similar to that described by McCallister et al. except for all n banks of the RAM reading to a respective parallel-input m-bit-wide latch, thereafter to side-load a respective m-stage shift register. The use of the extra m-bit-wide latch, although a simple modification to RAM structure, has profound effects upon the flexibility of RAM operation. In the prior art the RAM has been accessed by the VDP on a regularly recurring basis, but particularly with my RAM architecture this is not necessary to do. In my RAM architecture each bank needs to be read from once per m pixel display cycle, but does not need to be read from regularly every m pixels. As I describe particularly in application Ser. No. 710,295 this permits a RAM access protocol where the CPU has access without wait to the RAM more than (m-n)/m of the time. This is provided by VDP access being capable of limited waits, owing to all n of the m-stage shift registers being preceded by m-bit-wide latches with temporary storage capability.
Further the RAM architecture described in applications Ser. Nos. 710,292 and 710,295 can be modified to permit the banks to load their m-bit-wide output data parallelly or partially parallelly, as well as serially, to respective latches, thereafter to side-load respective m-stage shift registers. This permits a RAM access protocol where the CPU has access without wait to the RAM (m-1)/m of the time if the VDP regularly accesses the RAM. RAM access protocols where the CPU has even less restricted asses to the RAM are made possible by subjecting VDP access to limited waits, as described above.